With advancement in process geometries offered by ASIC foundries, System on Chip (SoC) designers have increased functionality by combining multiple chips into one. This approach improves performance and reduces cost.
The advanced capabilities utilized by design engineers typically result in SoCs having multiple CPU cores. Multiple CPU cores require significantly increased amounts of embedded memories, in many cases 4X that which was used in prior generation products. Compounding the problem, most embedded memories utilized today have a large cell size that contributes to an unnecessarily large die size. Current consumption and/or leakage are common issues.
SoC designers are constantly faced with the challenge of choosing between the various memory types offered by ASIC foundries, their product needs and competitive pressures. Typically used in embedded applications are old technologies like SRAM, EEPROM and eFLASH; each has its advantages, but along with those come significant weaknesses.
The table below illustrates the tradeoff and difficulties that designers have historically faced when making an embedded memory selection.
Today, Avalanche Technology’s pMTJ based STT-MRAM addresses these challenges, allowing for increased embedded memory needs, without making trade-offs or significantly increasing costs.
Avalanche’s technology is backed by an extensive intellectual property portfolio spanning from MTJ material and stack to circuit design and the deployment of such memories in a system level application. Avalanche’s STT MRAM is base layer agnostic and currently uses a standard CMOS process with few process steps to offer ease of integration and low cost.
Avalanche Technology has been developing next generation pMTJ based STT-MRAM for over five years. We’ve sought to address the shortcomings of existing memories while embracing the strength of each and thus created AvRAM, a next-generation memory that revolutionizes the embedded memory landscape. We look forward to working with your team to create exciting and better performing SoCs.