STT-MRAM Technology

A Powerful Non-Volatile Memory

Avalanche’s Spin Torque Transfer Magnetic RAM (STT-MRAM) utilizes a revolutionary spin current switching technology allowing for lower write current, smaller cell size, with excellent scalability. Utilizing proprietary Multi-Level Cell (MLC) techniques combined with a patented 3D stacking process, the cell size roadmap begins at 15F2 and extends below 1.0F2, less than 1/5th the size of any current memory device. These scaling innovations occur independently of CMOS lithography shrinks, which will occur in parallel to below10nm. This will lead to an unprecedented combination of low cost and performance features, creating opportunities for revolutionary system design utilizing STT-MRAM technology.

The core storage unit of Avalanche’s STT-MRAM is a perpendicular magnetic tunnel junction (p-MTJ) cell composed of a ferromagnetic-pinned layer, a dielectric barrier layer and another ferromagnetic storage layer. The magnetic orientation of the pinned layer is static and permanently fixed during the fabrication process, while the magnetic orientation of the storage layer is capable of switching from a parallel configuration with respect to that of the pinned layer (low resistance state, “0”) to an antiparallel configuration (high resistance state “1”) by applying an electric current through an MTJ cell. Thus, two binary states can be realized for digital data storage.

Avalanche’s leading-edge and proprietary pMTJ, from materials system to advanced integration scheme, deliver all the attributes required of a disruptive nonvolatile memory technology. High performance pMTJs, fast writing speed in sub nanosecond range and unlimited endurance (>1016 cycle), have been developed and integrated at chip level with 300 mm wafers, and is poised for commercial foundry transfer and low-cost volume production. The Avalanche pMTJ-driven STT-MRAM greatly enhances memory component/system performance and provides a clear path to a variety of products, from low power SoC and cache memories to storage class memory.

Avalanche is licensing its embedded MRAM technology to fab partners and major system OEMs. The embedded memory is called AvRAM™, and it enables up to a 6X reduction in die size per megabyte as compared to even the most advanced embedded SRAM used in microprocessors and chipsets today. Die area of SOC and ASICS are often comprised of significant embedded SRAM. With the adoption of AvRAM, partners can save between 35%-50% of overall die size. AvRAM is scalable well below 10nm and is able to be integrated with standard CMOS processes and low voltage transistors. Additionally, the technology is non-volatile and has no current leakage enabling very low standby power consumption with unlimited endurance. These attributes enable unique performance and functionality such as instant on, no memory loss, cyber security, longer battery life and no wear out and through an internal unified memory interface, dramatically simplifies system designs/architectures. AvRAM provides straightforward integration and manufacturing with existing logic processes. The memory integration occurs at the back end of the line (BEOL) after the completion of all logic processes.