Invited Talks, Papers and Conferences

2016

  1. "STT-MRAM Technology and Productization", (invited), NCCAVS Advanced Memory Meeting, Santa Clara, California, April 21, 2016.
  2. "Fully Functional 64Mb STT-MRAM Utilizing Advanced pMTJ on 300mm Wafers,"(invited), International Conference of the Asian Union of Magnetic Societies. Tainan, Taiwan, August 1-5, 2016.
  3. “Extreme Events in STT-MRAM Speed Retention and Reliability” (invited), SPIE Nanoscience + Engineer Symposium, San Diego, California, August 28-September 1, 2016.
  4. "Avalanche Technology, Leader in pMTJ Solutions", Flash Memory Summit, Santa Clara California, August 9-11, 2016.

2015

  1. "Fully Functional 64Mb pMTJ STT-MRAM Chips on 300mm Wafers", (invited), 2015 International Workshop: Spintronics VLSI, Sendai, Japan, Nov 20-21, 2015.
  2. "Fully Functional pMTJ STT-MRAM Chips with Portable Manufacturing and Robust Performance,"(invited), 3rd US Government Workshop on Magnetic Tunnel Junctions, College Park, Maryland, Nov 4, 2015.
  3. "pMTJ Driven STT-MRAM Sampling From 300 mm Process," Flash Memory Summit, Santa Clara, CA, August 9-11, 2015.
  4. "pMTJ Driven STT MRAM with 300mm Process," (invited) 2015 Intermag Conference, Beijing, China, May 11-15, 2015.
  5. "Spin-Orbitronics Memory Device with Matching and Self-reference Functionality," (IEEE. Trans. on Magnetics, vol. 51, no.11, 1401504, 2015), 2015 Intermag Conference, Beijing, China, May 11-15, 2015.
  6. "Unipolar Switching of Perpendicular MTJ for STT-MRAM Application," 2015 Intermag Conference, Beijing, China, May 11-15, 2015.
  7. “STT–MRAM: A Leading Emerging Nonvolatile Memory,” (invited) Huawei 2015 Annual Strategic Technology Meeting, Shenzhen, China, May 19-20, 2015

2014

  1. "pMTJ-Driven STT-MRAM Products with 300mm Process" — Canon Winter MRAM Forum, IEEE International Electron Devices Meeting, San Francisco, CA Dec. 16, 2014.
  2. "Perpendicular magnetic tunnel junction with thin CoFeB/Ta/Co/Pd/Co reference layer,” Applied Physics Letters 105 (19), 192403(1)-192403(5), 2014
  3. “pMTJ-Driven STT-MRAM and Its Thermal Stability Scaling," 2014 MMM Conference, Honolulu, Nov 3-7, 2014.
  4. "Perpendicular magnetic tunnel junction with ultra-thin reference layer," 2014 MMM Conference, Honolulu, Nov. 3-7, 2014.
  5. "Novel Read Method of STT-MRAM Multi-Level-Cell," 2014 MMM Conference, Honolulu, Nov. 3-7, 2014.
  6. "Impact of Ion Beam Etch (IBE) on TMR and Switching Current of pMTJ STT-MRAM Cells on 300mm Wafers," 2014 MMM Conference, Honolulu, Nov. 3-7, 2014.
  7. "MRAM Panel" — Flash Memory Summit, Santa Clara, CA, August 6, 2014
  8. "Life Beyond Flash: New Non-Volatile Memory Technologies" — Flash Memory Summit, Santa Clara, August 7, 2014
  9. "Different Dielectric Breakdown Mechanisms Between RF-MgO and Natural Oxidized MgO": Appl. Phys. Express 7, 083002-1 to 083002-4, 2014.
  10. "pMTJ Driven STT-MRAM": From Low Power Cache and SoC Memories to New Market Applications, Canon-Anelva MRAM Forum, San Francisco, July 9, 2014.

2013

  1. "Multi-level Perpendicular MTJ STT-MRAM With Controlled Edge Field", 2013 MMM Conference, Denver, Nov 4-8, 2013
  2. "Dramatic Reduction of Read Error through Pulse Width Control in Spin Torque Random Access Memory", 2013 MMM Conference, Denver, Nov 4-8, 2013
  3. "MRAM: The Next Storage Memory", Flash Memory Summit 2013, Aug. 12-15, 2013, Santa Clara Convention Center, Santa Clara, CA
  4. "STT MRAM Technology: Status and Outlook", The 3rd International Symposium on Advanced Magnetics Materials and Applications (ISAMMA), July 21-25, 2013, Taichung, Taiwan.
  5. "STT MRAM: Perpendicular MTJ Prospective", Panel discussion, 2013 5th IEEE International Memory Workshop (IMW), 26-29 May 2013, Monterey, CA.
  6. "Write Error Rate Investigation of Spin Transfer Switched Magnetic Tunnel Junction", The 3rd CSIS International Symposium on Spintronics-based VLSIs and The 11th RIEC International Workshop on Spintronics, Tohoku University, Jan.31-Feb.1, 2013 Sendai, Japan.
  7. "Investigation of Write Error Rate in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM)", 12th Joint MMM/Intermag Conference , Jan 14-18, 2013
  8. "Dramatic Reduction of Read Disturb Through Pulse Width Control in Spin Torque Random Access Memory", Applied Physics Letters 103 (14), 142419, 2013
  9. "Bit error rate investigation of spin-transfer-switched magnetic tunnel junctions", Applied Physics Letters 101 (14), 142406-142406-4, 2013

2012

  1. "STT -MRAM: Latest Advances and MTJ Roadmap", Canon-Anelva MRAM Forum, 12 December, 2012, San Francisco.
  2. "STT -MRAM Recent Progress and Roadmap", 2012 International Workshop on Information Storage/9th International Symposium on Optical Storage, 21-24 October, 2012, Shanghai, China
  3. "Write Error Rate in Spin Transfer Torque Magnetic Random Access Memory", SPIN Journal, Vol. 02 No. 3 pp12400, 2012
  4. "STT MRAM Recent Progress and Roadmap", 9th International Symposium on Advanced Gate Stack Technology, October 3-4, 2012, Saratoga, NY.
  5. "STT MRAM: Recent Strong Semiconductor Industry Traction", The 2nd CSIS International Symposium on Spintronics-based VLSIs and The 8th RIEC International Workshop on Spintronics, Tohoku University 2-3 Feb. 2012 Sendai, Japan.
  6. "STT MRAM: Recent Strong Semiconductor Industry Traction", IEEE 8th Annual Full Day Symposium – "Emerging Non-Volatile Memory Technologies", 6 April 2012, Texas Instruments Conference Center, 2900 Semiconductor Drive, Santa Clara, CA.

2011

  1. "Progress and Outlook for STT MRAM", 2011 Frontier of Spintronics /Nanoelectronics Workshop, April 24, 2011, Hsinchu Ambassador Hotel, Hsinchu, Taiwan.
  2. "Progress and Outlook for STT MRAM", Silicon Valley Magnetic Symposium Program, June 18, 2011, Cadence Design Systems Auditorium, 2655 Seely Avenue, San Jose, California.
  3. "Progress and Outlook for STT MRAM", Silicon Valley Magnetic Symposium Program, June 18, 2011, Cadence Design Systems Auditorium, 2655 Seely Avenue, San Jose, California.
  4. "Spin Programmable Storage Solutions", Flash Memory Summit 2011, Aug 11, 2011, Santa Clara Convention Center, Santa Clara, CA
  5. "Recent Progress and Roadmap for STT MRAM", The International Conference on Computer-Aided Design (ICCAD), Nov. 7-10, 2011, San Jose, California, USA.
  6. "Recent Progress and Roadmap for STT MRAM", New Non-Volatile Memory Workshop, Nov. 10-11, 2011, ITRI, Hsinchu,Taiwan.
  7. "STT MRAM: Recent Industry Traction", The 7th Taiwan International Conference on Spintronics (TICSpin), Dec. 2-5, 2011, "The Solas" spring resort, Taiwan.

2010

  1. "STT MRAM: Recent Progress and Market Positions", International Symposium on Integrated Functionalities (ISIF), June 13-16, 2010, San Juan, Puerto Rico.
  2. "Recent Advances and Market Positions of Spin Torque MRAM", The 21st Magnetic Recording Conference (TMRC 2010), Aug 16-18, 2010, University of San Diego, La Jolla, California, USA.
  3. "Recent Advances and Market Position of Spin-Torque MRAM", Asia-Pacific Data Storage Conference (APDSC'10), Oct. 27-29, 2010, Parkview Hotel, Hualien,Taiwan.
  4. "Latest Advances and Market Positions of Spin Torque MRAM", The 6th Taiwan International Conference on Spintronics (TICSpin), Dec.1-3, 2010, Taichung, Taiwan.

2009

  1. "Integrating Magnetic Tunnel Junctions on CMOS: the Challenges of STT- MRAM", June 9th, 2009 , UCLA, CA, USA
  2. "Integrating Magnetic Tunnel Junctions on CMOS: the Challenges and Successes of MRAM", 2009 International Magnetics Conference (Intermag), May, 4-8, 2009 , Sacramento, CA, USA
  3. "Spin Torque Transfer Driven Magnetoresistive Random Access Memory (STT-MRAM)", 2009 American Physics Society (APS) March Meeting, March 16-20, 2009, Pittsburgh, PA, USA
  4. "Integrating Magnetic Tunnel Junctions on CMOS: the Challenges and Successes of MRAM", The 5th Taiwan International Conference on Spintronics (TICSpin), Sep. 9-11, 2009, Taichung, Taiwan.