DOCUMENTS

1Gbit – 8Gbit Dual Quad SPI P-SRAM Memory

1Gbit – 8Gbit Dual Quad SPI P-SRAM Memory

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Revision F.4 - January 23, 2024

Latest Revision Changes

  • CR1 default for WREN was incorrectly stated as 10. It is 00.
  • CR2 default for latency was incorrectly stated as 0000. It is 8 cycles: 1000
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