1Gbit – 8Gbit Dual Quad SPI P-SRAM Memory
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Revision C - July 20, 2022
Latest Revision Changes
- Removed Performance Table
- Added Figures to ToC
- Added Tables to ToC
- Updated SDR Data Output Operation & Timing
- Updated DDR Data Output Operation & Timing
- Renamed from 88Ball to 96Ball (Included mechanical support balls)
- Added Extended Safe Operating Area as well as Normal Operating Conditions