Avalanche Technology’s Space Grade Ava-MRAM is capable of deterministic data commits. Traditional STT-MRAM stores its information within a Perpendicular Magnetic Tunnel Junction (pMTJ) whose underlying physics grants non-volatile writes. Ava-MRAM is engineered for byte-level write granularity and carries no complicated overhead to manage, enabling instant writes. For space missions of any type, ensuring your data stays intact should not be constrained by the memory hardware. While many technologies claim to be “Space Grade,” true Space Grade requires that 5 objective criteria be met simultaneously. Space Grade technology must:
- Survive radiation without disruption
- Retain data for the life of a mission
- Endure unlimited writes
- Commit data instantly
- Prove real space heritage
This blog covers the fourth pillar of Space Grade, COMMIT, qualifies the device’s ability to securely commit data in hostile environments including the power limited and high radiation environments of space.
The Memory Market Today
Selecting the best memory device for specialized applications is an important decision. Alternative radiation-immune, non-volatile memory technologies do not offer the same density found in Avalanche Technology’s Space Grade Ava-MRAM. For a space environment, reliable storage needs to also come in reasonable densities. Therefore, RRAM, FRAM, toggle MRAM will be excluded from the discussion. Today, Avalanche offers discrete memory devices up to 8 Gigabit while the other resilient memory devices mentioned come in densities ≤ 16 Megabit.
A memory technology’s ability to successfully commit data is a critical feature for high reliability applications. In the terrestrial setting, flash memory is chosen for its high density and performance. Flash storage gives the appearance of instantaneous commits through software abstraction. In reality, data remains in a vulnerable state while the internal flash management system takes data from a host and commits it to the flash memory cells. For NOR and NAND flash, this becomes non-determinism for data commits. This uncertainty poses a data loss risk in the hostile radiation and power constrained environment of space missions. Avalanche Technology’s Space Grade Ava-MRAM is capable of time-deterministic data commits ensuring data is securely stored with integrity and accuracy.
NOR and NAND
Functionally, both NOR and NAND flash operate using an erase-before-write procedure, a limitation of the charge-trap-based memory cell found in flash memory. NOR and NAND also require different levels of management to achieve reliability as storage. This inflates the total number of steps required to successfully commit data which ultimately increases the total time required. Furthermore, some flash management schemes, like garbage collection and bad sector management, introduce non-determinism for data writes.
Charge Trap NOR
Traditional charge trap NOR flash offers somewhat time-deterministic writes to its flash memory cells. In standard operating mode, the smallest unit of memory that can be written to is a page, typically between 4KB and 256 KB. Because of the erase-before-write limitation of flash cells, a whole page of memory needs to be erased before a program, or write, happens for even a single byte.
The biggest limiting factor for NOR flash writes is this erase step that occurs beforehand. Because of it, work arounds have been created to increase write performance for NOR flash. Incremental programming is one such scheme which allows for multiple programming operations within one erase cycle. In a page where there are programmed 1’s, individual bits can be programmed when being changed to 0’s. One downside to this technique is that the action can only be completed in one direction. For programming bits from 0’s to 1’s, the whole page has to be erased, setting us back to the original issue of long page erases. Another downside to this method is that it ruins ECC, meaning that precomputed ecc bits are invalidated unless they get recomputed. In normal operation, the error checking bits that get calculated for ECC occur before a page level write. Modern NOR often doesn’t allow incremental programming because of the data integrity risks of breaking ECC.
Flash memory cell degradation also increases the duration it takes for a write to complete. This occurs because of oxidative stress caused by aging and total write cycles on a flash memory cell. As oxidative stress builds, the number of electrical pulses required to complete a write increases. Ultimately, both the erase and program steps can have varying completion times associated with them.
NOR That Necessitates ECC
Another difference to consider is the requirement of ECC between low density and high density NOR flash. As previously mentioned, ECC adds additional delays to a data commit because of the extra steps required. Like standard NOR flash, a page of memory must first be erased before individual bits can be programmed. In many NOR flash architectures, the ECC engine calculates parity bits either during or after the data write, and in some implementations this requires an additional write operation to commit the ECC bits separately from the data. This can result in two write operations occurring for a single data commit, rather than one. The added delay of using ECC can limit the suitability of high density NOR flash for real-time applications with strict timing requirements.
NAND
NAND flash offers no determinism when it comes to data commits because of the greatly complicated management system required for NAND flash. The components required to manage the flash system include a NAND driver, ECC engine, bad block management, the flash translation layer, and a wear leveling mechanism. Once the host gives a write command to a NAND storage device and starts sending data, there is no guarantee on how long it will take for the data to be securely stored in the flash cells.
In NAND flash management, the various error events that could occur require differing amounts of time to recover from. This could range from milliseconds to seconds. Bad block management and sector remapping are examples of error management systems that NAND must perform. These introduce non-determinism in the operation of a NAND storage device and are impossible to predict.
Just like NOR flash, NAND flash requires an erase before a write can occur, but with no possibility of using incremental programming. In NAND, the smallest unit of data that can be written is a page like NOR. Unlike NOR flash, the smallest unit for an erase is a block, which consists of multiple pages. Consider a NAND device with 64 pages in a block. In the hypothetical worst case scenario, where every page within a block contains valid data, 63 pages would need to be rewritten alongside the original target-page write. This additional data shuffling and requirement to rewrite adjacent pages in a block increases the delay in committing data.
Space Grade Ava-MRAM
Avalanche Technology’s Space Grade Ava-MRAM offers a completely deterministic data commit whereas flash does not. When writing data to Ava-MRAM, the host has access to the physical address space of the device. This difference eliminates the need of a translation layer from logical to physical addressing. The Ava-MRAM is also not limited by erase-before-write operations since the pMTJ cell can be programmed bidirectionally at the byte level. Most importantly, no additional management schemes, like wear garbage collection, are required between the host and the MRAM device. This ease of interfacing with the device, the transparency offered to the host, and the instantaneous nature of data commits position Ava-MRAM as the best solution for securely committing data into non-volatile storage. Altogether, Avalanche Ava-MRAM easily satisfies the Commit pillar of a Space Grade device.
Integrating Ava-MRAM Reliability With NAND Capacity
A beneficial synergy arises when Ava-MRAM is used in conjunction with NAND. A storage solution with an Ava-MRAM buffer in front of a NAND flash array improves data commit reliability. Any write operation to NAND could become irrecoverably corrupted, particularly in the high-radiation environment of space. For example, during a write to NAND, the target block could be in an unknown bad state. Normally, mitigations like data scrubbing are enough to verify and correct the integrity of a write. This read-verity-correct process relies on the ECC engine and the ECC bits. But, when inadvertently writing to a bad block, or to a block damaged in the middle of the write process, the data corruption could be too much to be fixed with ECC.
Ava-MRAM can be used as a secure storage buffer to prevent this type of data loss event. Because of the high reliability of Ava-MRAM, all incoming capture data can be securely committed to it as a buffer. Then, the buffer can start offloading the data to a larger NAND flash array for bulk storage. This ensures an accurate copy of the data exists until it can be safely stored into the higher capacity NAND array. In any other case where there was no reliable buffer to hold onto the data, the data would have been permanently lost. A combination of Ava-MRAM and NAND offers a high density storage solution with reliable data commits.
Achieving Space Grade
A hostile environment like space requires storage with instantaneous data commits. On the market today, there are few memory solutions that offer this level of deterministic data commits. But of those solutions, none are offered at the same density of Avalanche’s Ava-MRAM. The Commit pillar of Space Grade follows a simple principle: data sent by the host to storage should reliably be secured without questions on the integrity. The software and hardware layers that flash devices have between the host and storage hinder the reliability of securely storing data in a deterministic manner. Avalanche Ava-MRAM offers the system integrator a storage solution as transparent as SRAM but with the benefits of non-volatility, radiation immunity, and high storage density. The instantaneous commitment of critical data while in a hostile environment, like space, is a guarantee no other memory solutions can offer.
Ultimately, there is no one requirement of Space Grade that stands above the rest. While many technologies claim to be “Space Grade,” true Space Grade requires that 5 objective criteria be met simultaneously. Space Grade technology must survive radiation without disruption, retain data for the life of a mission, endure unlimited writes, commit data instantly, and prove real space heritage. In space systems, a technology that survives radiation but loses data, wears out over time, delays data commitment, or lacks flight heritage is not Space Grade. Partial compliance leads to failure. Avalanche reaffirms its leadership as the only provider of true Space Grade memory, delivering solutions that meet all five non-negotiable criteria required for space missions: Survive, Retain, Endure, Commit, and Prove. Avalanche Space Grade Ava-MRAM uniquely delivers radiation immunity, permanent data retention, unlimited endurance, deterministic nanosecond writes, and proven flight qualification, without tradeoffs.
