Resources
Documents
Space Grade
Change

64Mbit – 128Mbit Dual QSPI MRAM Memory

Receive Updates to this Datasheet

Optional: Enter your email address to be notified when this Datasheet is updated.

Revision C.4 - June 10, 2025

Latest Revision Changes
  • Added Clock edge use for DDR
  • Updated Power Up Ramp for VCC and VCCIO
  • Updated Table showing HBP [2:0 H-H-H]
  • Output drive strength default value changed to C0
  • Added package height impact due to reballing to Lead.
Download Latest Version
Sign up for our quarterly newsletter.
Avalanche Technology Inc.
3450 West Warren Avenue,
Fremont, CA 94538
(510) 897-3300
info@avalanche-technology.com
©2024 Avalanche Technology | All Rights Reserved | Privacy Policy