New High-Density MRAM Devices Provide Flexible and Robust Write Protection Schemes for Use as Bootable Memory as well as for Working Memory
Fremont, California, August 15, 2022 – Avalanche Technology, the leader in next generation MRAM technology, announced it is joining the Xilinx Radiation Test Consortium (XRTC), an organization comprised of industry, academia and government partners, pooling resources to characterize and mitigate radiation-induced effects in FPGAs, along with providing additional design enablement for improved utility in harsh environments such as outer space. One of this community’s more substantive challenges in recent years has been lacking bootable memory solutions of sufficient density and radiation resilience, particularly for today’s more demanding processors and FPGAs, such as Xilinx’s Versal platform with a 1Gb image size. Avalanche’s Gen 3 Space Grade MRAM-based solutions are being increasingly validated by the Defense Industrial Base (DIB) and Commercial Space ecosystem for their ability to realize the longstanding promise of MRAM as an ideal candidate for Unified Memory Architectures based on their uniquely high-reliability, endurance (1016) and density (1Gb to 8Gb options available today), and low power (10mA per 1Gb).
At the annual XRTC meeting being held at The Aerospace Corporation in El Segundo, CA on September 20th-22nd, 2022, Avalanche Technology General Manager Paul Chopelas will be presenting these enabling solutions including write protection methods that allow this singular memory to be used for booting FPGAs and processors with firmware and RTOS images as well as working memory for scratchpad or temporary over the air firmware updates, all without the need for external ECC or wear leveling. Included in this platform rollout of Avalanche’s High Density Dual-QSPI Space Grade family and Boot Module will be critical design support packages such as reference designs (on their website now), quick start guides, and modules that allow Avalanche’s devices to plug into Xilinx’s VCK190 development kits.
“As a new member of the XRTC, Avalanche continues to listen to the needs of the DIB and Commercial Space ecosystem, providing impactful solutions with commercial agility. With high reliability built into the DNA of our MRAM-based solutions and architectural decisions responsive to community needs, this Boot Module will allow a much more flexible and SWAP-C (Size, Weight, Power and Cost) optimized architecture,” said Danny Sabour, Vice President of Marketing and Business Development at Avalanche Technology. “Instead of having banks of memory, each often requiring radiation mitigation circuitry including legacy non-volatile memory to support boot functions, and then SRAM, DRAM and NAND to support working memory and storage, our Gen 3 speed, density and endurance, along with robust write protection schemes, give designers much more optionality for design simplification and consolidation.”
“From all reports, Avalanche has the coolest part of the year, finally a good-density MRAM that is inherently radiation resilient and seems tailor-made for booting Versal devices. We’re dying to get beam-test results on this new non-volatile memory,” said Gary Swift, leader of the XRTC and CEO of Swift Engineering and Radiation Services, LLC. “I think, based upon inputs I’m receiving from key players in the A&D ecosystem, that this Gen 3 Dual-QSPI Space Grade family is the long-awaited answer to all of our Xilinx space players’ prayers.”
Avalanche Gen 3 Persistent SRAM
The Gen 3 Parallel and Dual-QSPI MRAM-based Persistent SRAM device series is offered as a standard product in various density options from 1Gb to 8Gb and has asynchronous SRAM-compatible read/write timings. Data is always non-volatile with Avalanche’s industry-leading 1016 write cycle endurance and 1,000-year retention (at 85°C). Both sets of interface options are available in a small footprint FBGA packages that are sub 0.70 grams. The devices are offered in extended (-40°C to 125°C) operating temperature range with a JEDEC qualification flow, where every device goes through a 48-hour burn in before being shipped to customers. Datasheets, models, development kits and reference designs are all available on Avalanche’s website. There are also additional qualification screening options available through partners.
More information about Avalanche P-SRAM products is available at https://www.avalanche-technology.com/products/discrete-mram/space/.
About Avalanche Technology
Avalanche Technology Inc. is the leader in the next generation Perpendicular STT-MRAM technology, accepted as the front-runner to replace traditional Flash and SRAM for unified memory architectures in future SOC systems, delivering high performance and low power at 55, 40, 28 and 22nm with scalability to 14nm. With a proven STT-MRAM portfolio at multiple geometry nodes combined with an intellectual property portfolio of over 300 patents and applications, Avalanche Technology is delivering on the promise of enabling the next generation of scalable embedded unified memory architecture for use in GPUs, MCUs, DSPs, ASSPs and ASICs, making it the true “Next Generation MRAM Company”. For more information, visit us online at https://www.avalanche-technology.com.
About Xilinx Radiation Test Consortium (XRTC)
Since 2002, Xilinx Radiation Test Consortium (XRTC) partners have pooled resources through the XRTC to characterize and mitigate radiation-induced effects in FPGAs with the goal of boldly increasing their use in harsh radiation environments, esp. outer space. The XRTC was founded in 2002 by NASA/JPL and Xilinx to evaluate re-configurable FPGAs for aerospace applications. The Consortium brings together top experts from industry, government, and academia to test and characterize radiation effects and mitigation techniques for re-configurable FPGAs. The XRTC strives to 1) provide independent and unbiased testing and characterization of radiation effects and mitigation techniques in re-configurable FPGAs; 2) facilitate industry cooperation and collaboration in the testing of re-configurable FPGAs; and 3) enable public awareness and access to test results and publications.