DOCUMENTS

64Mbit – 128Mbit Dual QSPI MRAM Memory

Receive Updates to this DatasheetOptional: Enter your email address to be notified when THIS data sheet is updated.

Revision B.1 - May 01, 2024
Latest Revision Changes

Updated tPU Specification: VCC Power Up to First Instruction

Updated latency timing for 108MHz (8 to 12 cycles).

GET OUR NEWSLETTER

3450 West Warren Avenue, Fremont, CA 94538
(510) 897-3300
info@www.avalanche-technology.com